Dynamic Random Access Memory (DRAM) is a type of volatile random access memory that stores each bit of data in a separate DRAM cell. A DRAM integrated circuit (IC) includes an array of DRAM cells interconnected by rows of word lines and columns of bit lines. Each DRAM cell must be periodically refreshed to ensure that the information it stores is not lost when it is not powered.
FIG. 1 is a circuit schematic which illustrates a conventional one transistor/one capacitor (1T/1C) dynamic random access memory (DRAM) cell 2, and will be described with reference to FIG. 2, which illustrates two conventional 1T/1C DRAM cells 2, 4 in plan view, and with reference to FIG. 3, which illustrates one of the 1T/1C DRAM cells 2 of FIG. 2 along cross section 3-3 of FIG. 2. The DRAM cell 2 consists of a metal oxide semiconductor field effect transistor (MOSFET) 50 in series with a storage capacitor 70 that stores electric charge representing a binary bit of data.
The MOSFET 50 is commonly referred to as an access transistor since it controls read and write access to the storage capacitor 70. The access transistor 50 includes a gate structure 17, 20 that is interposed between a source and a drain 30, 40. The gate structure 17, 20 includes a gate electrode 20 that is formed overlying a gate oxide layer 17. The gate electrode 20 of the access transistor 50 is coupled to a word line 4 of the DRAM cell 2. The gate oxide layer 17 serves as insulator between the gate electrode 20 and a channel of the access transistor 50. As illustrated in FIG. 3, the source and drain 30, 40 are formed in a semiconductor substrate 9 and spaced apart by an active body region 35. The channel is defined in the active body region 35 of semiconductor substrate 9 between the source and drain 30, 40. A bit line 10 is coupled to the source 30 of the access transistor 50.
One type of storage capacitor that is commonly employed in a DRAM cell is a trench capacitor. A trench capacitor is a three-dimensional structure formed within a deep trench etched into a semiconductor substrate. FIGS. 2 and 3 illustrate one implementation of a trench storage capacitor 70 that includes an upper electrode 76 separated from a lower electrode 72 by a thin dielectric layer 74. The access transistor 50 serves as a switch for controlling the charging and discharging of the storage capacitor 70, writing information onto the storage capacitor 70, and reading information from the storage capacitor 70. As illustrated in FIGS. 1 and 3, the upper electrode 76 of the storage capacitor 70 is coupled to the drain 40 of the access transistor 50 such that the access transistor 50 can control the flow of current between the bit line 10 and the storage capacitor 70, and vice-versa. By controlling the voltages applied to the source electrode 30 and the gate electrode 20, writing and reading operations can be performed.
Data is written by raising the voltage applied to the word line 4 to turn the access transistor 50 on, and applying a high or low voltage level to the bit line 10 to write a high or low voltage level onto the storage capacitor 70. Lowering the voltage applied to the word line 20 turns the access transistor 50 off thereby trapping charge on the storage capacitor 70 and hence storing the data.
To read the DRAM cell 2, the bit line 10 is precharged midway between high and low voltage levels, the access transistor 50 is turned on by raising voltage applied to word line 4, and the charge stored on the storage capacitor 70 is allowed to flow onto the bit line 10, which creates a small signal voltage on the bit line 10, which can then be detected by a sense amplifier (not illustrated). When the amount of charge stored at the storage capacitor 70 is above a certain level this can be interpreted as a logic one (1) state, and when the amount of charge stored by the storage capacitor 70 is below the level this can be interpreted as a logic zero (0) state. More precisely, data is read by (1) precharging the bit line 10 midway between the high and low levels, (2) raising the voltage applied to the word line 4 to turn the access transistor 50 on, and (3) sensing the voltage change (commonly referred to as “signal voltage” (Vsignal)) on the bit line 10 that is caused by sharing charge between the storage capacitor 70 (Cstorage) and parasitic capacitance (Cbitline) associated with the bitline 10. The signal voltage (Vsignal) can be determined as shown in Equation (1),Vsignal=0.5*Vstorage*Cstorage/(Cbitline+Cstorage)  (1),
where Vstorage is the voltage difference between the stored high and low levels on the storage capacitor 70, and Cbitline is the parasitic capacitance of the bit line 10 including input capacitance of the sense amplifier (not shown). The extent to which the actual voltage difference (Vstorage) between the stored high and low levels on the storage capacitor 70 approaches the voltage swing on the bit line 10 (i.e., bit line-high voltage (VBLH) minus bit line-low voltage (VBLL), which is usually zero), is determined by the current provided by the access transistor 50, the value of the storage capacitor 70, and the amount of time allocated for the transfer of charge between the bit line 10 and the storage capacitor 70.
As new generations of DRAM are designed, technologists continue to search for new ways to reduce the size of the DRAM cell and/or to improve performance of the DRAM cell. One approach to reducing DRAM cell-size involves completely eliminating the storage capacitor 70. FIG. 4 is a circuit schematic which illustrates a conventional one transistor (1T) DRAM cell 102, and will be described with reference to FIG. 5, which illustrates two conventional 1T DRAM cells 102, 104 in plan view, and with reference to FIG. 6, which illustrates one of the conventional 1T DRAM cells 102 of FIG. 5 along cross section 6-6 of FIG. 5. The DRAM cell 102 consists of an access transistor 150 that performs both a state storage function and an access control function so that a separate storage capacitor is not needed. Instead, the active body region 135 of the access transistor 150 is used for data storage.
To explain further, the access transistor 150 is formed in and on a silicon-on-insulator (SOI) structure 102 that includes a carrier substrate 105, a buried oxide layer 107 and a thin semiconductor substrate 109. The gate structure 117, 120, source 130 and drain 140 are similar to those described above with respect to FIGS. 1-3 except that they are formed on and in the semiconductor substrate 109 that overlies the buried oxide layer 107. The active body region 135 of the access transistor 150 has an inherent parasitic capacitance associated with it because it is formed in the thin semiconductor substrate 109. During operation, the active body region 135 is left electrically floating, which is different from a bulk transistor where body is connected to fixed body voltage. The active body region 135 is left in a floating state so that it can be charged up or discharged. The well-known “floating body effect” leads to the development of charge in the active body region 135 that can be used to store “1” or “0” binary data states in the DRAM cell 102. For example, by applying control signals to word line 104 and bit line 110, majority charge carriers can be accumulated in the active body region 135. This property can be used to write data to DRAM cell 102. In addition, because the threshold voltage (VTH) required to turn on the access transistor 150 changes depending upon the amount of charge stored in the active body region 135, changes in the threshold voltage (VTH) of the access transistor 150 can be used to read data states stored by the DRAM cell 102.
For instance, when the access transistor 150 is an NMOSFET, the active body region 135 is P-type semiconductor material, in which “holes” are “more abundant” and evenly distributed throughout the active body region 135. The DRAM cell 102 can write and store a logic one (1) or high data state by accumulating excess holes in the active body region 135. When the access transistor 150 is turned on by applying a voltage to the gate that exceeds the threshold voltage of the access transistor 150, electrons will flow from the source 140 to the drain 140. As charges balance at the p-n junction between the active body region 135 and the drain 140, holes accumulates in the active body region to balance the charge on each side of the junctions with equal and opposite charges. The DRAM cell 102 can write or store logic zero (0) or low data state when an excess of holes are not present in the active body region 135.
To write and store a logic one (1) or high data state, majority carrier holes are accumulated in the active body region 135 by applying a voltage to the gate 120 and positively biasing the drain region 140 with respect to the source region 130 to generate excess holes and produce a residual positive charge in the active body region 135. The threshold voltage (VTH) required to turn on the access transistor 150 changes based on the amount of holes (i.e., positive charges) stored in the active body region 135. In particular, this residual positive charge increases the threshold voltage (VTH) required to turn the access transistor 150 on because more voltage must be applied to the gate to repel holes. As will be explained below, this increased threshold voltage (VTH) can be detected and interpreted as a logic one (1) since lower threshold voltage (VTH) decreases the drain-to-source current (Ids) flowing through the channel.
By contrast, to write and store a logic zero (0) or low data state in the DRAM cell 102, from the absence of an abudance of holes in the active body region 135 decreases the threshold voltage (VTH) required to turn the access transistor 150 on because less voltage must be applied to the gate 120 to repel positive chrages. As will be described below, this decreased threshold voltage (VTH) can be read or interpreted as a logic zero (0) since higher threshold voltage (VTH) increases the drain-to-source current (Ids) flowing through the channel.
Unlike the conventional DRAM cell 2 illustrated in FIGS. 1-3 that implements a trench capacitor, a read operation does not involve directly measuring the quantity of charge present in the active body region 135, but instead the change in the threshold voltage (VTH) required to turn on the access transistor 150 can be used to determine whether the memory cell 102 is storing a logic one (1) or high versus a logic zero. The drain-to-source current (Ids) will either increase or decrease depending on the threshold voltage (VTH), which, as noted above, changes depending on the charge stored in the active body region 135. An increase in the drain-to-source current (Ids) can be interpreted as a logic one, whereas a decrease in the drain-to-source current (Ids) can be interpreted as a logic zero. To read the data stored in the DRAM cell 102, a small pulse is applied to the gate electrode 120 of the access transistor 150 via wordline 104, which turns the access transistor 150 on and causes a drain-to-source current (Ids) to flow into the bit line 110. A current sense amplifier (not illustrated) compares drain-to-source current (Ids) generated by the access transistor 150 to a reference current provided by a reference cell (not illustrated). From that comparison, it may be determined whether DRAM cell 102 is storing a logic high (relatively more majority carriers contained within body region 135) or logic low data state (relatively less majority carriers contained within body region 135).
Although the DRAM cell 102 has a smaller cell size than a conventional DRAM cell 2, the DRAM cell 102 has diminished data-retention characteristics since a smaller number of charges can be stored in the active body region 135. In general, the capacitance of the DRAM cell 102 is 100 times smaller than a conventional DRAM cell 2 that implements a trench storage capacitor 70.
Notwithstanding the density improvements provided by 1T DRAM cells, data-retention time of DRAM cells continues to be an important consideration since it directly affects power dissipation and memory speed.
As such, it is desirable to provide improved DRAM cells that use the floating body effect to store information and methods for fabricating such DRAM cells. For example, it is desirable to improve charge storage capacity (i.e., capacitance) of such DRAM cells to increase data retention time, improve disturb characteristics and to improve their reliability. Furthermore, other desirable features and characteristics of the present invention will become apparent from the detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.